1. Field of the Invention
This invention generally relates to a PLL (Phase-Locked Loop) circuit for synchronizing with a carrier wave, and more particularly to a PLL circuit, such as a Costas loop type DPLL (Digital PLL) circuit, suitable for detecting a carrier wave in an FM multiplexed data broadcasting in which digital signal such as an ARI (Autofahrer Rundfunk Information) signal for identifying traffic information or an RDS (Radio Data System) signal for transmitting a message of digital data is multiplexed to FM signal.
2. Description of the Prior Art
As a traffic information system for relieving a traffic snarl, there is known an ARI broadcasting system. In the ARI broadcasting system, a sub-carrier of 57 kHz is constantly multiplexed into FM radio wave of broadcasting station so as to identify the station which is broadcasting traffic information. In addition, in that system, a DK signal and a BK signal, obtained by amplitude-modulating the sub-carrier by predetermined frequencies, are multiplexed into the radio wave so as to provide information relating to a commence or end of the traffic information, or a region in which traffic information is broadcasted.
As a similar system, there is known an RDS system in which digital data identifying broadcasting stations, etc., are multiplexed into FM radio wave using a sub-carrier of 57 kHz. Data to be multiplexed in the RDS system is configured by a plurality of groups consist of 104 bits data, and various messages mainly used for selection of broadcasting station are standardized. The transmission rate of RDS data is 1.1875 kbit/sec, and RDS data is encoded by a differential encoding. Then, clock signal of 1.1875 kHz is modulated by a bi-phase shift keying using encoded data. Further, sub-carrier of 57 kHz is modulated by a carrier suppressed amplitude modulation using modulated data of bi-phase shift keying. Double sideband (DSB) signal of the modulated data is multiplexed to audio data, and the multiplexed data is transmitted. Sub-carrier of RDS data is designed so as to be in phase or in orthogonal phase (shifted by 90 degrees) with third harmonic of a pilot signal (19 kHz) indicating a stereo broadcasting. When it is required to maintain coexistence of ARI signal and RDS modulated signal, the two signals are multiplexed so that the frequencies thereof equal to each other and the phase relation of them becomes in orthogonal with each other (shifted by 90 degrees).
FIG. 1 shows a frequency spectrum in which RDS signal and ARI signal (S.sub.2) are multiplexed to FM audio signal (S.sub.1). FIG. 2 shows a basic construction of a receiver of FM multiplexed broadcasting (RDS). As seen from FIG. 1, RDS modulation signal is allocated around the frequency band of sub-carrier of 57 kHz with small magnitude level so as not to disturb audio signal in audio frequency band.
In the FM multiplexed data receiver, as shown in FIG. 2, an antenna 51 receives the transmitted radio wave of FM multiplexed broadcasting. From the radio wave received by the antenna 51, a desired broadcasting station is selected by a front end 52. The signal selected by the front end 52 is successively supplied to an IF (Intermediate Frequency) amplifier 53, an FM detector 54 and a multiplexer 55, and output from the multiplexer demodulating circuit (MPX) 55. In a case where the audio signal is a stereo signal, audio signals of Left-channel and Right-channel are output from the MPX 55. The detected signal from the FM detector 54 is also supplied to a filter 56 in which RDS modulation signal having frequency component of sub-carrier 57 kHz is extracted. On the basis of the extracted signal, an RDS decode/clock generate unit 57 generates a clock signal and demodulates RDS data using the generated clock signal. The demodulated RDS data is supplied to a controller 60 via a group.multidot.block period/error detect unit 58 and an error correction unit 59. The controller 60 analyzes code information of the RDS data and stores it into a RAM 61. Further, the controller 60 controls the selection of broadcasting station in the front end 52 in accordance with instruction from an operation unit 62.
RDS data is reproduced by the above-described receiver by demodulating RDS modulation signal. However, this RDS modulation signal cannot be demodulated by a simple PLL circuit. Namely, the frequency of the sub-carrier cannot be extracted by a simple PLL circuit because DSB signal thereof has such a characteristics that the phase of the sub-carrier reverses at zero-cross points of envelop of the DSB signal. Therefore, a Costas loop type DPLL circuit suitable for digital signal processing is utilized as a PLL circuit for synchronization of sub-carrier in the demodulating circuit of RDS modulation signal.
FIG. 3 shows a construction of a Costas loop type DPLL circuit. As shown in FIG. 3, the Costas loop type DPLL circuit 70 includes multipliers (D-FF) 71 and 72, a phase comparator 73, a sequential loop filter 74 and a voltage controlled oscillator (VCO) 75. The VCO 75 includes a fixed oscillator 75a and a variable divider 75b. The variable divider 75b divides clock signal output from the fixed oscillator 75a in accordance with the output signals of the sequential loop filter 74 to produce a first reference signal B having the same frequency as the input signal and in phase with the input signal, a second reference signal C having the same frequency as the input signal and whose phase is shifted by 90 degrees from that of the input signal and a synchronization control signal E synchronous with the first reference signal B. As seen from FIG. 3, the RDS modulation signal input via the input terminal I.sub.in is converted to a square wave by a comparator 69, and the converted signal A is supplied to the multipliers 71 and 72 in the Costas loop type DPLL circuit 70.
The first reference signal B is supplied to the multiplier 71 as a sampling signal while the second reference signal C is supplied to the multiplier 72 as a sampling signal. The A/D converted signal A from the comparator 69 is sampled by the multipliers 71 and 72, and the sampled signals are supplied to the phase comparator 73. The phase comparator 73 has two output terminals respectively output phase precedence signal and phase lag signal, and these output signals are supplied to the sequential loop filter 74. The phase comparator 73 outputs, from one of the two output terminals, pulses in phase with the sub-carrier and representing the phase precedence or phase lag. The sequential loop filter 74 counts the pulses output from the phase comparator 73 to control the variable divider 75b. In response to the control signal from the sequential loop filter 74, the frequency of the reference signals output from the variable divider 75b approaches to the frequency of the sub-carrier, and finally coincides with the frequency of the sub-carrier. When the frequency of the signal from the variable divider 75b coincides with the frequency of the sub-carrier, the Costas loop type DPLL circuit 70 becomes locked. In this locked state, the multiplier 71 outputs an in-phase synchronizing signal in phase with the sub-carrier while the multiplier 72 outputs an orthogonal synchronizing signal in orthogonal phase with the sub-carrier. Thus synchronizing signals are detected.
The above phase comparator 73 includes an EX-OR circuit 73a, an inverter circuit 73b and AND circuits 73c and 73d. The output signals of the multipliers 71 and 72 are supplied to the EX-OR circuit 73a. A phase comparison signal D output from the EX-OR circuit 73a is input to the AND circuit 73c as it is and input to the AND circuit 73d after being inverted by the inverter 73b. The AND circuits 73c and 73d responsive to the synchronization control signal E output a positive-direction phase difference signal F and a negative-direction phase difference signal G, respectively.
The sequential loop filter 74 is constructed as shown is FIG. 4. The positive-direction phase difference signal F and the negative-direction phase difference signal G, respectively indicating phase precedence and phase lag, are stacked in N-bit registers 81 and 82, and the sum of the signals is stacked in the M-bit register 84 via an OR circuit 83. If one of the N-bit registers 81 and 82 becomes full before or simultaneous with the M-bit register 84, the N-bit registers 81 and 82 output a reset pulse to reset all the registers. When the Costas loop type DPLL circuit 70 is in locked state, the M-bit register 84 tends to be full and frequency of reset pulse decreased. Therefore, the synchronization detection is stabilized. This type of filter is called "N-before-M filter" and generally used in DPLL circuits.
In a DPLL circuit, RDS modulation signal is required to be highly accurately demodulated, and hence it is necessary that phase comparison signal produced by phase comparator is highly accurate. However, the above described Costas loop type DPLL circuit detects phase difference by sampling the input signal A for one period, and hence the phase comparator outputs same phase comparison signal regardless of the value of the phase difference. This will be described below with reference to FIGS. 5A-5G and FIGS. 6A-6G. FIGS. 5A-5G show timing charts of respective signals A to G in a case where phase difference between the input signal A and the first reference signal B is large. As seen from FIGS. 5A-5G, when the phase difference between the input signal A and the first reference signal B is large, the output signal of the multiplier 71 becomes high level and the output signal of the multiplier 72 becomes high level, and hence the phase comparison signal D becomes low level. Therefore, the AND circuit 73d outputs no pulse and the positive-direction phase difference signal F maintains low level. Alternately, the AND circuit 73c outputs, as the negative-direction phase difference signal G, pulse signal synchronous with the synchronization control signal E. The sequential loop filter 74 detects this pulse signal and outputs the control signal to make the DPLL circuit locked state.
FIGS. 6A-6G show timing charts of respective signals A to G in a case where the direction of the phase difference between the input signal A and the first reference signal B is same as the case of FIGS. 5A-5G but the phase difference value is smaller than that case. As seen from FIGS. 6A-6G, when the phase difference between the input signal A and the first reference signal B is small, the phase comparison signal D becomes low level, and the output signals of the AND circuits 73c and 73D are identical to that in the case of FIGS. 5A-5G.
As mentioned above, the Costas loop type DPLL circuit shown in FIG. 3 is capable of producing phase difference signal of only high or low level. In other words, this kind of DPLL circuit can only discriminate whether the phase of the reference signal is preceding or lagged, and cannot detect how much the phase difference value is. For this reason, in this DPLL circuit, the VCO circuit varies the frequency of reference signal for a fixed value regardless of the value of the phase difference. Therefore, in some cases, the VCO circuit excessively varies the frequency of the reference signal even though the phase difference is small. This makes the performance of the DPLL circuit unstable.